1. Field of the Invention
The present invention relates to a phase-locked loop (PLL), and more particularly, to a PLL for utilizing a fractional-N PLL as a signal source for generating an oscillation signal.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram of a prior art analog PLL 100. As shown in FIG. 1, the PLL 100 comprises a phase/frequency detector (PFD) 110, a charge pump 120, a low-pass filter 130, a voltage-controllable oscillator (VCO) 140, and a frequency divider 150. The PFD 110 is utilized for detecting a phase error or frequency difference between an input signal S_in and a feedback signal S_fb. The charge pump 120 is utilized for generating an output current according to a detection result generated from the PFD 110. The low-pass filter 130 is utilized for generating a control voltage CV according to the output current. The VCO 140 is utilized for generating an oscillation signal S_vco according to the control voltage CV. The frequency divider 150 is utilized for performing a frequency dividing operation upon the oscillation signal S_vco to generate the feedback signal S_fb.
The prior art PLL 100 faces a dilemma when it comes to circuit design. In order to maintain the reliability of the PLL 100, the loop bandwidth of the PLL 100 should be designed to be narrow enough to avoid the effect of jitters of the input signal S_in. However, this will reduce the ability of the PLL 100 to track the input signal S_in and to suppress the effect of jitters of the oscillation signal S_vco generated by the VCO 140. The dilemma becomes more serious when the required frequency of the oscillation signal S_vco differs from the frequency of the input signal S_in by a large degree. For example, when the PLL 100 is applied into a control circuit in an LCD device, the frequency of the input signal S_in (i.e. a horizontal synchronous signal Hsync) is almost 15 KHz˜100 KHz; however, the required frequency of the oscillation signal S_vco is almost 13 MHz˜210 MHz. The required frequency of the oscillation signal S_vco may be several thousand times that of the horizontal synchronous signal Hsync. In this situation, it is obvious that the prior art analog PLL 100 cannot simultaneously overcome the problems of poor system reliability, and poor ability to track an input signal and suppress jitters resulting from the oscillator.